MAX2392ETI+T【PDF 27/33 页】IC RECEIVERS ZERO-IF 28TQFN-EP

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W-CDMA/W-TDD/TD-SCDMA Zero-IF Receivers

Detailed Description

With the exception of the analog-input AGC, all func-

tionality of these direct-conversion receivers can be

controlled through the 3-wire serial interface

(SPI?/QSPI?/MICROWIRE? compatible).

Register Definition

All devices in this family have two programmable 20-bit

registers: the configuration register (CONFIG) and the

control register (OPCNTRL). The MAX2391/MAX2392/

MAX2393/MAX2401 have two additional programmable

20-bit registers: the main PLL divide register (RFM) and

the reference PLL divide register (RFR). The 4 least sig-

nificant bits of the data sent are the register’s address.

The 16 most significant bits are used for register data.

All registers contain a few don’t care bits. These can be

either 0 or 1 and do not affect operation. Tables 1a and

1b provide a register summary. Data is shifted in MSB

first. When CS is low, data is shifted with the rising

edge of the clock. When CS transitions to high, the shift

register is latched into the register selected by the con-

tents of the address bits. Power-up defaults for the four

registers are shown in Table 2.

The RFM register sets the main-frequency divide ratio

for the RF PLL. The RFR register sets the reference-fre-

quency divide ratio. The RF LO frequency can be

determined by the following:

RF LO frequency = f REFIN x (RFM / RFR)

where f REFIN is the external input reference frequency

MICROWIRE is a trademark of National Semiconductor Corp.

SPI and QSPI are trademarks of Motorola, Inc.

for the MAX2390–MAX2393, MAX2401.

The operation control register (OPCNTRL) and the con-

figuration register (CONFIG) are used to program the

receiver for the appropriate mode of operation. See

Tables 3 and 4 for the function of each bit.

The test register is used to set the receiver in factory

testing mode. It should only be programmed at receiver

turn-on with the word 0370 (hex) for MAX2390–MAX2393,

MAX2401 and 2370 (hex) for MAX2396/MAX2400.

Power Management

Bias control is distributed among several functional sec-

tions and can be controlled to accommodate different

power-down modes as shown in Table 5.

The IC has three bias states: SHUTDOWN, IDLE, and

ON. SHUTDOWN can be asserted by either a hardware

control line ( SHDN ) or by bit 5 of the operation control

register (OPCTRL. SHDN ). When the serial interface is

used to shut down the part, an internal linear regulator,

with IQ ≈ 90μA, stays functional to keep the serial inter-

face operational. Use the SHDN logic-control pin to

bring quiescent current below 10μA. Register bit set-

tings maintain their values after a hard shutdown, pro-

vided CS remains high. IDLE mode disables the LNA,

I/Q mixers, and baseband circuitry, but keeps the serial

interface and synthesizer operational, dropping quies-

cent current to 11.5mA. The entire receiver is ON when

SHDN is high and OPCNTRL. SHDN and

OPCNTRL. IDLE bits (MAX2390–MAX2393, MAX2401)

or the IDLE pin (MAX2396/MAX2400) are set to 1; the

typical supply current is 32mA.

Table 1a. Register Defintion (MAX2390–MAX2393, MAX2401)

REGISTER

NAME

MSB

20-BIT REGISTER

DATA 16 BITS

LSB

ADDRESS 4 BITS

B15 B14 B13 B12 B11 B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

A3

A2

A1

A0

RFM

RFR

OPCNTRL

CONFIG

0

0

1

1

0

1

0

1

1

1

1

1

1

1

1

1

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